1. Field of the Invention
The present invention generally relates to silicon on insulator technology microprocessor designs, and more particularly to a new structure and method for electrically characterizing submicron MOSFET devices and passive structures.
2. Description of the Related Art
In order to electrically characterize submicron MOSFET devices and passive structures on advanced technology sub 0.13 μm channel length devices incorporating thin gate oxide films (less than about 2 nm), low-k dielectric films (both spin on low-k dielectric films and PECVD low-k films) and silicon-on-insulator FEOL (front end of the line) technology, focused ion beam drilling may be used. The drilling occurs through low-k dielectric films, which typically have dielectric constants of less than about 3.3, examples of which are available commercially, and other dielectric films (i.e., PECVD silicon oxide, LPCVD silicon, HDP nitride, LPCVD nitride, TEOS, BPSG, PSG, polymide, and other conventional dielectric materials having dielectric constants roughly in the range of about 4 to 5) and requires focused ion beam (FIB) gas assisted etching (GAE) (using such gases as XeF2, Cl2, Br2, TMCTS with Oxygen).
In the prior art, this GAE etch “drilling” of a hole is accomplished with FIB apertures 65 μm and larger using FIB beam currents greater than 100 ρA (nominally) to react with a tungsten metal source heated above 52° C. for gas sublimation reaction. The incident 30 kV (and higher acceleration voltage) FIB electron beam with the gaseous tungsten (delivered with nozzles) produces tungsten ions that “coat” or deposit tungsten on the surfaces in the region of interest.
Typically, in this prior art, the electron beam currents associated with these aperture sizes are as follows:
Aperture SizeBeam Currents (assuming 50 kV Accelerating Beam)60μm91.8ρA75μm209.2ρA100μm569.0ρA150μm2,071.0ρA200μm4,761.0ρA250μm8,658.0ρA300μm3,679.0ρA350μm19,704.0ρA400μm26,596.0ρA
Emerging technologies (sub 0.13 μm channel length devices, thin gate oxide films (less than about 2 nm), low-k dielectric porous films (both spin on low-k dielectric films and PECVD low-k films) and silicon-on-insulator) cannot be subjected to high FIB beam currents in electron or charge neutralizing modes.
In FIB electron beam modes with beam currents greater than 91.8 ρA, undesirable rupturing of thin gate oxides results as well as charging/discharging of the MOSFET devices, especially with “floating body” effects in partially depleted SOI structures. Damage to passive structures, especially with low-k dielectric films occurs due to beam induced charging. In addition, with the FIB operation in a charge neutralized mode (i.e., “flood gun”), the resulting imaging resolution is degraded, and prevents the drilling operation with submicron (<0.18 μm) spacings and/or feature sizes to occur without shorting/leakage paths introduced from the gallium beam. The resolution imaging capability of the FIB in the charge neutralized mode is likewise reduced.
In addition, the deposited CVD tungsten or platinum reaction with apertures of 60 μm and greater produces an “overspray” or deposition in an area greater than the submicron hole feature itself producing additional shorting/leakage paths to adjacent device features/passive structures.
Silicon on Insulator (SOI) designed microprocessors offer first order benefits of lower power operation, reduced junction capacitance, and higher device densities; all of which combine in providing significant improvements in device performance and faster circuit level speeds. Integrating SOI technology with lower resistance (<2 μΩ-cm) copper Back End of Line (BEOL) interconnections instead of aluminum-copper BEOL interconnection (>3 μΩ-cm resistance) offers further enhancements in microprocessor performance.
Electrical measurements of the sub 0.25 μm sized NFET and PFET devices contained in the embedded cells of these SOI designs pose new demands in developing alternative techniques and methods for both electrical characterization and physical analysis.
MOSFET devices in prior art SOI designs do not tie the FET's body to the source implant but instead are allowed to “float” because of the insulating layer used in this technology. Conventional methods of scanning electron microscopy, transmission electron microscopy, or focused ion beam microscopy, where energetic (>30 kV) electron or ion beams are employed, can produce unwanted effects affecting electrical and physical analysis.
Newer electrical characterization techniques such as atomic force microscopy imaging of submicron device features and physical AFM electrical probe contact measurements may be necessary when characterizing junction areas above the SOI insulating layer.
Scanning capacitance microscopy is another technique successfully employed in pinpointing specific submicron device features in the embedded array cells. Specific sites less than 0.3 μm have been identified this way that correlate to anomalous electrically measured results. Subsequent transmission electron microscopy (TEM) accuracy is further enhanced by this pinpointing technique. This successful localization permits enhanced TEM analysis involving electron energy loss spectroscopy (EELS) to detect the presence of low atomic number elements.
The use of conventional FIB parameters to deposit chemical vapor deposited tungsten or platinum probe pads as an aid in assisting submicron device probing or circuit deletion/isolation of levels near the SOI insulating layer may induce unwanted charge build-up as well as gallium ion leakage inimical to SOI designs.
Similarly, changes in TEM sample preparation techniques must be adopted to avoid introducing induced artifacts and physical damage. In those instances where samples are thinned via FIB sectioning, the same concerns exist as described earlier (i.e., introduction of unwanted charge buildup and/or gallium induced leakage paths).
Specific features in CMOS latching circuits of SOI designs can now be pinpointed by using these modified electrical techniques, aided by the use of scanning capacitance microscopy and enhanced TEM physical analysis/sample preparation techniques.
To minimize the unwanted effects affecting electrical and physical analysis, modifications in the electrical characterization techniques as well as changes in FIB circuit analysis and sample preparation must be made to avoid the introduction of misleading electrical measurement results and artifacts in physical analysis results.
Generally, for SOI technology, and specifically, for example, for low-k dielectric-based technology, strained-silicon junction technology, and very thin (less than about 2 nm) gate dielectric technology, there is an absence of techniques for device characterization and pinpointing defects. Submicron devices require characterization for design verification, and current techniques such as FIB assisted probing will damage features. Thus, there is a need to characterize without damaging the device and features.